Calculate Effective Adress and Real (physical) or Absolute adress

An idea is forming on what is what in the machine. this is an Example from the X86 assembly language and C fundamentals book, that I have elaborated on, and more or less found out what the words mean .

Find Effective Address, And Real Adress.

DS = 1100h,

DISPLACEMENT = -126d

SI = 0500h

Using the REAL adressing mode of 20 bits adress, determine the physical memory adress for the instruction below, is the assignment . The Real adress is where the byte resides within the RAM, in Legacy terms a location between 0 - FFFFF. The EA effective adress is the location of the stored byte inside each respective 64KB segment, CS, DS, SS or ES.

MOV DISPL [SI] , DX

1. Dec to Hex . Convert -126d to hex.

2. Invert the displacement of -126d by 2s compliment. Since the displacement is Signed and in this case the number is negative . 

3. Add DISPL to SI (Source Index) to obtain EA (Effective Adress).

4. Shift the DS (Data Segment) by multiplying it with 10. Intels increased Segment Memory Instruction Set 8086 from 1976. Then add the EA to DS to obtain REAL PHYSICAL (absolute) adress.

Convert - 126d to Hex

126 / 16 = 7, Reminder 14

7    / 16 = 0, Reminder 7

Hex       = 7 (14) = 7Eh = 007Eh

Find 2s compliment

  0               0               7               E

15-0          15-0          15-7           15-14

  F               F               8               1

(2s compliment)                        + 1 for Horus

---------------------------------------------------

  F               F               8               2

==============================

Hex DISPLACEMENT invert = FF82h

Obtain Effective Address

EA = DISPLACEMENT + SI

        F      F      8      2  : 2s complimet DISP

+      0      5      0      0  : SI Source Index

         |      |      |       2

         |      |      8

         |    F+5               :  F+5 = 15 + 5 = 20.

         |      4                    Then 20 – 16 = 4 . Then 1 to carry.

        1                         :  Carry moves the value up one

         |                             wheighted position, rightwards.

         |           

      F+1                       :  F+1 = 15 + 1 = 16 - 16 = 0

                                      Then 16 - 16 = 0. Then 1 to carry.

1                                 :  Carry to trunc. removed from nibble.

--------------------------

1      0      4      8      2     =  0482h  =  EA Effective Address

REAL Address = DISP + SI + DS

DS = 1100h

Notice that 1100h is multiplied by 10, due to increased instruction set ( F FFFF)

1100h * 10 = 11000h.

Notice that the EA effective adress retains its position to the right near the LSB (Least Significant Byte). and a 0 is added at the MSB (Most Significant Byte) to the left . The Segment Register is shifted 4 bits toward the MSB.

    1    1    0    0  «0»   : DS, The last zero is special.

                                   Intel added this to the segments.

  «0»   0    4    8    2     : EA, The first zero is also shifted.

                            2

                      8

                4

          1

    1

---------------------------

    1    1     4    8    2 = REAL address. Or PHYSICAL adress

=============== or ABSOLUTE Adress.

I have been struggeling with this for some time and it came to me when I used this method from converting Hex to Binarys

Converting from any Radix to BIN

Depending on what you want to convert what into, there are several methods. Here are some examples . sometimes division and reminder is used, but it turns out Bitshifting can also be used. It is also important to keep track of the wheighted positions of the 1`s 10`s and 100`s position.

HEX to BIN 

Value in hex = 1E3h

1 = 0001b

E = 14d = 1110b

3 = 0011b

     100`s. 10`s. 1`s.

1 : 0001

E : 0000 1110

3 : 0000 0000 0011b

=   0001 1110 0011b  Sum this up horizontal the usual way..

Bin to Decimal

= 0 + 0 + 0 + (1*2^8) + (1*2^7) + (1*2^6) ...continue on next line
     + (1*2^5) + 0 + 0 + 0 + (1*2^1) + (1*2^0) =

= 0+0+0+256+128+64+32+0+0+0+2+1= 483_decimal

Bin to Octal, group the binary to sections of 3 units, ( reverse the process for Oct to Bin)

000 111 100 011

  0     7     4     3 = 743_octal

Bin to Hex, Group the binary in sections of 4, called Nibbles. (Reverse the process for Bin to Hex)

0001 1110 0011

   1    14(E)   3      = 1E3_hex

Bin to BCD. The BCDs (Binary Coded Decimals) use groups of 4 bits called a nibble, allowing a count to 9. When value 9 is exeeded one uses a method called "Exess-6" addition to shift the Carry over to the MSB, to transform ordinary binarys into BCD binarys. 

BCD 9  = 1001

BCD10 = 0001 0000

Calculate the binary number of 12d into BCD
    0 0 0 0 1 1 0 0 = 12d
 +            0 1 1 0 = exess 6
 = 0 0 0 1 0 0 1 0 = BCD value of 12d

Dec to BCD. Decimal value is split int groups of 4 starting on the LSB
     4         8        3       Decimal value
  0100   1000  0011 = BCD value 

Hex to BCD.  I have to go from Hex to Decimal to get the BCD. I didnt figure how to do a direct Hex to BCD. Radix_16 to Radix_10 . Then Radix_10 to Radix_9 . 

1 E 3 = (1 * 16^3) + (14 * 16^2) + (3 * 16^0)
1 E 3 = 256 + 224 + 3 = 483d

   4          8          3      = Decimal value of 1E3
0100    1000    0011   = BCD grouping of the Hex value 1E3.

DEC to BIN
Convert the value 500 decimal value to binary. I start by subtracting the total value of a Exponent of 2. Then close in to the largest exponent that can subtract the desired number Minuend without making the Differance or result negative. I then repeat the process unitl the Exponents have reached 2^0.

500 - 2^9 = 500 - 512 = - 12 ( Subtrahend 512 is too large, value is negative )

500 - 2^8 = 500 - 256 = 244 (Bin = 1 ) MSB . Value is positive .
244 - 2^7 = 244 - 128 = 116 (Bin = 1)
116 - 2^6 = 116 - 64 = 52     (Bin = 1)
52 - 2^5 = 52 - 32 = 20         (Bin = 1)
20 - 2^4 = 20 - 16 = 4           (Bin = 1)
4 - 2^3 = 4 - 8 = -4               (Bin = 0) Value is negative.
4 - 2^2 = 4 - 4 = 0                (Bin = 1)
0 - 2^1 = 0 - 2 = -2               (Bin = 0)
-2 - 2^0 = -2 -1 = -3             (Bin = 0) LSB Least Significant Bit

Binary value = 1 1 1 1 1 0 1 0 0 b = 500d

To convert from DEC to HEX via BIN is another method than converting from Dec to Hex directly using division and the Reminder. Because as shown above, start grouping the binarys in groups of 4 starting on the LSB, then Trace the numbers vertically into the 1`s position, 10`s postion and 100`ds position.

                  100       10         1
                8 4 2 1-8 4 2 1-8 4 2 1
                ---------------------------
                                        0 1 0 0
                             1 1 1 1
                 0 0 0 1
                ---------------------------
    500d =      1          F          4      Hex



From BX register to EA effective adress
In the register you write one value of 16 bits to BX, or a 8bit value to BL and BH. Max value for each 8bit register is a value of 255d, or FFh . AX sets some accumulator flags and BX is used for accessing memory. The following method enables you to translate HEX into binarys at a fast glance.

MOV BH, 159

MOV BL, 246

First translate the values into binarys
159 - 2^7 = 31
31-2^4 = 15
15-2^3 = 7
7-2^2=3
3-2^1=1
1-2^0=0
Binarys of 159 = 1 0 0 1 1 1 1 1

246 - 2^7 = 118
118-2^6=54
54-2^5=22
22-2^4=6
6-2^2=2
2-2^1=0
Binary of 246 = 1 1 1 1 0 1 1 0

                                                     BX
                  BH                                                             BL
                 159                                                            246
          1 0 0 1 1 1 1 1                                           1 1 1 1 0 1 1 0

   1 0 0 1               1 1 1 1                             1 1 1 1               0 1 1 0
     
        9                        F                                     F                        6

16 bit HEX = 9FF6
This adress value constitute the EA effective adress. And is added with the Segment register to form the Real adress into RAM. the Ram slot may however return a Byte 8bit, a word 16bits, a a double word 32bit or a quad word of 64bits, determined by its purpose . To write this REAL memory adresse on a X86-64 system running Windows 10, has proven itself to be a headache of magnitude. I am thinking of obtaining a Windows98 either on a new machine or format a partition of my NTSF HDD into FAT32. The DMA Direct Memory Access chip on my particular system Intel P-ATA 8237 is backwards compatible to 8086, Motherboard being BF43DP. The NT Kernel used in since Windows 2000, Vista, win 7,win 8,win 10 uses strictly Protected Mode and the Paging memory system is totally different from what the DOS Kernel used in the era win 95/98/ME, these older machines enable REAL mode. Assembly for 20Bits computers is regarded as a Dinosaur interest of Embedded Systems enthusiasts, I guess. what needs to be mentioned is that Assembly is the favoured language for I/O sensors, Adressing memory, BIOS, Kernel, enabling the keyboard, mouse, monitor, printer and tablets. Take a look at what Language your Telephone is written in. Assembly ! In my opinion the only use for C and C++ is to access ASM modules.

Intel Assembly page : http://www.intel-assembler.it/portale/indice.asp

A great idea for the industry would be a Multiprocessor that had 1 CPU in 16 bit, another in 20Bit and another in 32 bit , and the last in 64bit. All CPUs photographed on the same MultiBit Processor wafer . Then Partition the Hard Disks in FAT16, FAT32, NTFS, for the different files and Operating Systems. Well ... for fun certainly, why else ?

Microsoft on FAT 32 : https://support.microsoft.com/en-us/kb/154997

8086 Numbering system : http://www.eie.polyu.edu.hk/~enyhchan/8086_ASM_Tutorial.pdf

The Physical Adress means adress to RAM, The Adress to a RAM location is formed in the CPU Registers. The CPU is divided 2 main parts, the 1st unit is the EU «Execution Unit» with the GPR (General Purpose Registers ) : AX, BX, CX, DX, 16 bits wide however subdivided into High and Low of 8 bits each. SP, BP, SI and DI are 16 bits wide registers and form the adress into each respective Segment, these registers form the EA Effective Adress or "Adress into Segment". The CPUs 2nd unit is the BUI (Bus interface Unit) that contains the Segment Registers CS, DS, SS, ES, and IP, forming the arithmetic Segment 4bit shift addition. These are each one line of 16 bits. The BUI also has a ALU that sums up the 16bit GPR and 16 bit Segment register with a 4 bit shift forming a 20 bit adress that connects to RAM, revealing the stored Byte that resides at the Real adress in RAM. In RAM the segments appera as 64KB volumes of data content.

In the processors EU and BUI the Adresses to RAM is formed.  The Segments is as they appear in the RAM is accessed witin a range of 65535 values. The 1 MB of Legacy RAM supposedly can room 16 such segments. Segment 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F. If each segment in RAM can store 2^16 = 65535 address values. Then 16 segments in RAM * 65535 address values = 1 048 576. (1MB)
With the Segments available to Assembly only CS, DS, SS, ES is available for the programmers data content and the other 12 registers are called "Internal Communication Registers" consuming the largest part of the 1MB total. For instance the BIOS occupy two whole segments E and F, of 128KB. The BIOS is copied from a slow chip ROM on the Motherboard to fast RAM in a process called "BIOS Shadowing".  Extension cards occupy Segments D and E. Video BIOS from the Graphix card occupy Segment A and B. Notice that in Intel terminology its the BIOS that has a 1 MB of address space, The Operative System DOS and User Programs has only 640KB adressable memory locations in total on the 8086. Considering the size of the Assembly registers CS (.CODE code segment), DS (.DATA data segment) , SS (.STACK stack segment), ES (.EXTRA extra segment) . The IP ( Instruction Pointer ) is a Register of 16bits in the BUI , and I interpret that as the program can not exeed 65535 lines of code . The programmers distributed adress space is practically 64KB * 4 = 256KB !

The Legacy 1 MB BIOS area .
Each 16 segments of 2^16 = 65535 = 64KB memory locations.
Segment F , E : BIOS Shadow.
Segment D , C : Option ROM or Expantion Rom , PCIe
Segment B , A : SM RAM or VGA buffer. MMIO.
Segment 1 - 9 : would contain the DOS, and the CS, DS, SS, ES, and IP
Segment 1     : 8 bit Hardware and Software Interrupts . Int 15h = 21d

Pdf : Intel P43 or P4 series chipset .
See page 57. to see the organisation of Adresses into 1MB legacy RAM.

Video : BIOS Session 2 - Legacy Region

Text : http://www.bioscentral.com

Text : http://stanislavs.org/helppc/bios_data_area.html

Book : The BIOS Companion: The book that doesn't come with your motherboard!

An example. presume I want to store a pixels colour that is 16 bit in RAM adress 11170h. That is the equal of 70 000d. It has come to my attention that a Physical Adress can be reached in many was, as long as the Register and Segments sum up the RAM adress value. If I want to access a stored byte in RAM on Physical adress 70 000d, that practically means I can not be inside of RAM segment 1 ( adress value 0 - 65535 ) . I have to be in segment 2, somewhere between adress 65535 - 131070. The practical interpretation of the calculations below, is that one may benefit from having a static Segment Register value, and change the GPR by displacements. since the CPUs of this generation performs one calculation per line.

Ex. Store word in RAM location 1 1 1 7 0 hex

EA    =    * 1 1 7 0    (Base pointer and Displacement . Offset)
Seg   =    1 0 0 0 *
Real  =    1 1 1 7 0


EA    =    * 0 1 7 0
Seg   =    1 1 0 0 *
Real  =    1 1 1 7 0


EA    =    * 0 0 7 0
Seg   =    1 1 1 0 *
Real  =   1 1 1 7 0

EA   =   * 0 0 0 0
Seg  =   1 1 1 7 *
Real =   1 1 1 7 0

The concept of Adressing bytes to Memory or RAM is still a partially philosopical concept to me. However I imagine and think it works along these lines. the question was basically why is it called adressing 1 MegaBYTE, When a 20bit system adresses practivally 1 million "adress values". The question that followed was, how large are the stored bytes in RAM. Each Adress value must extract a Byte, a Word (2 bytes) or longer . One can store a Byte of 8 bits, as a character (letter or symbol) or a number value using the Adress combinations of GPR (General Purpose Registers) and Segment Register, suppose the adress allows 20bit.

Now imagine that 8bit character is replaced by Pixel on the screen, If the colour is to change between 256 rainbow colour then you would want an 8bit, 2^8 = 256 numerical values to define that colour. The 20bit adress must extract a 8bits stored value from the RAM into a Register. The RAM must have a minimum of 8 wires on the Bus between the CPU and RAM, if arranged in Parallell. Now if I desire a 16 bit rainbow colour that shade from black to white. The byte stored must be a Word or a double byte, that is a colour value between 0 - 2^16 = 0 - 65 535 colour values. It would be reasonable to adress a Video card for Colours with wide Bus (32 to 64bit) and the numerical calulations on another chip .

Then imagine a 4bit CPU with 2^4 = 16 adress values. locating 16 adresses in the RAM. then imagine that each value in Ram is not a byte of 8bits ( that usually is for ASCII character symbols). but 64bits value. This would theoretically adress 16 pixels that each had 2^64 colour values ! Now how many pixels do you need to fill your screen ? Horizontal  x Vertical : VGA 640x480, HD 1920x1080 or 4K 4096x2160 .

Only Numerical arithmetical values needs to be signed, neither colours nor characters needs to have a signed bit. Not accounting for additive and subtractive Colour mixing, nor Additive or Subtractive audio Synthesis ! Additive Colur is like mixing oil paint on a palette, mix the Primary colours, blue Yellow and Red, and it gets a dark brown colour . Subtractive colours is having a disk with the primary colours Blue, Yellow and Red, spin the wheel and the colour is white !

What determines a computer systems "bit name", like a 8Bit CPU or a 16Bit VPU. First I thought it was the number of bits on the GPR ( General purpose Registers) then later the Segment registers. the AL and AH in both 16bit, 32bit and 64 bit are in 8bits, forming a unsigned value of 2^8=256 values or 0 -255. both registers AL and AH can form a unsigned value up to 2^16 = 65536 . Only after inspecting the Datasheet of the 8086 I think I understand why the computer is called in 8086 case a 20 bit. there is 16 parallell value pins and 4 additional Segment Pins, making it a total of 20 pins, therefore enabling an access up to 2^20 = 1MB. I then calculated over the number of bits and found out that this 20bit system actually can access alot more space. If each bit has a parallell line from the CPU it would adress up to 2^16bitGPR + 16bitSEG= 2^32 = 4.2Billion adresses . I then realised one has to recreate the CPU architecture into a 32 parallell bus line from the CPU, 16bits for the GPR and 16Bits for the Segments thus making it ia 32Bit processor ! I then played with the idea, and it can be seen that one can have a 4bit GPR, and have 60 bit segments, Making the machine adress up to 2^64 = 1.8E19 adress spaces. However the largest value you can type in on the keyboard would be 2^2 = 4 !!! Then I could reverse the idea having the GPR to have 60 pins in parallell, and have only 2 registers. Could they both be considered 64bit machines ? Or would the first be a 4bit machine accessing 4.2billion adress spaces, and the other be a 64Bit machine. The numerical calculations would be unsigned 1.8E19 in the EXA number range. But only 2 Segments. You want a decent number to be entered into the GPR, most likely 32Bit number for calculations, that reqires atleast 32parallell pins on the CPU. The segments pins comes in addition.

The 8086 has a tidy set of 16 adress wires and 4 segments wires making it a 20Bit machine. The segments are actually selected from a 2bit logic on leg S3 and S4, selecting between the DS (11), CS (10), SS (01) or ES (00) segments, S5, has something to do with the IF instruction or command. And the S6 is always 0 in Minimum mode .

Datasheet 8086 : http://www.ece.cmu.edu/~ece740/f11/lib/exe/fetch.php?media=wiki:8086-datasheet.pdf

However the 80386DX has 32Adress and value pins (D0 - D31) and additional 32 segment adress pins (A0-A31), actually giving it 64 parallell wires !

Datasheet 80386DX : http://pdf.datasheetcatalog.com/datasheet/Intel/mXtuvqv.pdf

To access a memory of 1 megabyte one must multiply 65535 * 16. Making it F FFFF. the last F has to be the Segment memory Intel added to get 1 MB .

Looking at the 8086 Chip it has it seems 16 legs or pins for parallell bytes (AD0 - AD15) for data and adressing, along with 4 pins for adressing only, named (A16/S3 - A19S6). Maybe this would be the Segment memory Intel added ? Counting the parallell wires from the chips legs it adds to 16 + 4 = 20 wires wide signal bus, making it 2^20. If all of these control logic connected to each line preforms a 0 and a 1 ( each number is hard wired ! Like any other value in everyday life. If the object  does not exist, neither does it have a value. An object being either mechincal, a physical force of any kind or a figment of imagination, existing as an emotion or a thought in your brain, all has value for it exists, How much influence these items has, depends on the Value attributed to them.) Then it would result in :

( It would make sense if the Registers are ordered something like this .... )

AL, BL, CL, DL : multiplexed on wires AD0 - AD3

AH, BH, CH, DH : multiplexed on wires AD4 - AD7

EAX, EBX, ECX, EDX : multiplexed on wires AD7 - AD15

multiplexed means one or two specific register at a certain clock cycle,

however all the register use the same wires.

same frequency, same volts, therefore "adressing" in binary "Data Selector".

 -------------------------Adress and Data--------------- Segment Adress

AD0-AD3     AD4-AD7    AD8-AD11    AD12-AD15     A16/S3-A19/S6

     1111            1111            1111            1111                    1111  

= FFFF F = 1 MB